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| THIS SPEC IS OBSOLETE Spec No: 38-07096 Spec Title: CY26112 One-PLL General Purpose Clock Generator Sunset Owner: IJA Replaced by: N/A CY26112 One-PLL General Purpose Clock Generator Features * Integrated phase-locked loop * Low skew, low jitter, high accuracy outputs * Frequency Select Pin * 3.3V Operation with 2.5 V Output Option * 16-TSSOP Part Number CY26112 Outputs 4 Input Frequency 14.7456 MHz Benefits Internal PLL with up to 333 MHz internal operation Meets critical timing requirements in complex system designs Dynamic frequency selection Enables application compatibility Industry standard package saves on board space Output Frequency Range 2 x 3.6864 MHz, 2 x 33/66 MHz (selectable) Logic Block Diagram Pin Configurations 3.6864 3.6864 XIN XOUT OSC. Q VCO P CY26112 16-pin TSSOP XIN VDD AVDD OE AVSS VSSL NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK4 CLK3 VSS N/C VDDL FS LCLK2 PLL OUTPUT MULTIPLEXER AND DIVIDERS FS 33/66 33/66 LCLK1 OE VDDL VSSL VDD AVDD AVSS VSS Output LCLK1 LCLK2 CLK3 CLK4 Pin 8 9 14 15 Default Frequency 3.6864 3.6864 33/66 (selectable) 33/66 (selectable) Unit MHz MHz MHz MHz Cypress Semiconductor Corporation Document #: 38-07096 Rev. OBS * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 02, 2004 CY26112 Summary Name XIN VDD AVDD OE AVSS VSSL NC LCLK1 LCLK2 FS VDDL NC VSS CLK3 CLK4 XOUT[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Reference Input Voltage Supply Analog Voltage Supply Output Enable, OE = 0 three-state; OE = 1 active Analog Ground LCLK Ground No Connect - Reserved 3.6864 MHz Clock output 1 at VDDL level 3.6864 MHz Clock output 2 at VDDL level Frequency Select Pin FS = 0: 33 MHz, FS = 1: 66 MHz LCLK Voltage Supply (2.5V or 3.3V) No Connect - Reserved Ground Clock output 3-33 MHz/66 MHz Clock output 4-33 MHz/66 MHz Reference Output Absolute Maximum Conditions Parameter VDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL Electro-Static Discharge AVSS 0.3 VSS 0.3 VSS 0.3 2 Min. 0.5 Max. 7.0 7.0 125 AVDD + 0.3 VDD + 0.3 VDDL +0.3 Unit V V C V V V kV Recommended Operating Conditions Parameter VDD VDDL TA CLOAD fREF Description Operating Voltage Operating Voltage Ambient Temperature Max. Load Capacitance Driven Reference Frequency 14.7456 Min. 3.0 2.375 0 Typ. 3.3 2.5 Max. 3.6 2.625 70 15 Unit V V C pF MHz Note: 1. Float XOUT if XIN is externally driven. Document #: 38-07096 Rev. OBS Page 2 of 5 CY26112 DC Electrical Characteristics Parameter[1] IOH IOL IOH IOL VIH VIL CIN IIZ IVDD IVDDL IVDDL Parameter[1] DC t3 t3 t4 t4 t5 t9 t10 Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current Supply Current Supply Current Supply Current Description VOH = VDD 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VOH = VDDL 0.5, VDDL = 2.5V VOL = 0.5, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD OE and FS Pins OE and FS Pins AVDD/VDDCurrent VDDL Current (VDDL = 3.6V) VDDL Current (VDDL = 2.625V) 5 25 7 5 Min. 12 12 8 8 0.7 0.3 7 Typ. 24 24 16 16 Max. Unit mA mA mA mA VDD VDD pF A mA mA mA AC Electrical Characteristics Name Description Duty Cycle is defined in Figure 2; t1/t2 @ 50% of VDD Rising Edge Slew Rate Output Clock Rise Time, 20% 80% of VDD/VDDL=3.3V Rising Edge Slew Rate Output Clock Rise Time, 20% 80% of VDDL = 2.5V Falling Edge Slew Rate Falling Edge Slew Rate Skew Clock Jitter PLL Lock Time Output Clock Fall Time, 80% 20% of VDD/VDDL=3.3V Output Clock Fall Time, 80% 20% of VDDL = 2.5V Delay between related outputs at rising edge Peak to Peak period jitter Min. 45 0.8 0.6 0.8 0.6 Typ. 50 1.4 1.2 1.4 1.2 250 350 3 Max. 55 Unit % V/ns V/ns V/ns V/ns ps ps ms t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t2\. t3 80% t4 CLK 20% Figure 2. Rise and Fall Time Definitions. Note: 2. Not 100% tested. Document #: 38-07096 Rev. OBS Page 3 of 5 CY26112 Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD AVDD 0.1 F GND Ordering Information Ordering Code CY26112ZC Package Name Z16 Package Type 16-Pin TSSOP Operating Range Commercial Operating Voltage 3.3V Document #: 38-07096 Rev. OBS Page 4 of 5 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26112 Document Title: CY26112 One-PLL General Purpose Clock Generator Document Number: 38-07096 REV. ** OBS ECN NO. 107331 294816 Issue Date 08/28/01 See ECN Orig. of Change CKN RGL Description of Change New Data Sheet To Obsolete the DS Document #: 38-07096 Rev. OBS Page 5 of 5 |
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